`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/05/2021 04:33:33 PM
// Design Name: 
// Module Name: mainControl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mainControl(
    input clk,
    input rst,
    input myen,
    input key_start_stop,
    input key_last,
    input over,
    input [3:0] work0,
    input [3:0] work1,
    input [3:0] rest0,
    input [3:0] rest1,
    output reg [3:0] LD0,
    output reg [3:0] LD1,
    output reg [3:0] LD2,
    output reg en,
    output reg rst_n,
    output reg en_cnt
    );
    parameter 
    S0 = 4'b0000,
    S1 = 4'b0001,
    S2 = 4'b0010,
    S3 = 4'b0011,
    S4 = 4'b0100,
    S5 = 4'b0101;
    reg [3:0] cstate,nstate;
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            cstate <= S0;
        end
        else if(myen)
            cstate <= nstate;
    end
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            nstate <= S0;
        end
        else if(myen)
            case (cstate)
                S0: if (key_start_stop==1) begin
                    nstate <= S1;  
                end
                S1: if (key_start_stop==1 && over==0 && key_last==0) 
                        nstate <= S2;  
                    else if(over==1 || key_last==1)
                        nstate <= S3;
                S2: if (key_start_stop==1 && key_last==0) 
                        nstate <= S1;  
                    else if (key_last==1) 
                        nstate <= S3;
                S3: if (key_start_stop==1) begin
                    nstate <= S4;  
                end
                S4: if (key_start_stop==1 && over==0 && key_last==0)
                        nstate <= S5; 
                    else if(over==1 || key_last==1)
                        nstate <= S0; 
                S5: if (key_start_stop==1 && key_last==0) 
                    nstate <= S4;  
                    else if (key_last==1) 
                        nstate <= S0;
            endcase
    end

    always @(posedge clk or posedge rst) begin
        if (rst) begin
            LD0 <= 0;
            LD1 <= work0;
            LD2 <= work1;
            en <= 0;
            rst_n <= 1;
        end
        else if(myen) 
        begin
            case (cstate)
                S0: begin
                    LD0 <= 0;
                    LD1 <= work0;
                    LD2 <= work1;
                    en <= 0;
                    rst_n <= 0;
                end
                S1:begin
                    LD0 <= 0;
                    LD1 <= work0;
                    LD2 <= work1;
                    en <= 1;
                    rst_n <= 1;
                end
                S2:begin
                    LD0 <= 0;
                    LD1 <= work0;
                    LD2 <= work1;
                    en <= 0;
                    rst_n <= 1;
                end
                S3:begin
                    LD0 <= 0;
                    LD1 <= rest0;
                    LD2 <= rest1;
                    en <= 0;
                    rst_n <= 0;
                end
                S4:begin
                    LD0 <= 0;
                    LD1 <= rest0;
                    LD2 <= rest1;
                    en <= 1;
                    rst_n <= 1;
                end
                S5:begin
                    LD0 <= 0;
                    LD1 <= rest0;
                    LD2 <= rest1;
                    en <= 0;
                    rst_n <= 1;
                end
            endcase
        end
    end
    always @(posedge clk or posedge rst) begin
        if(rst)
            en_cnt <= 0;
        else
            if (over==1 && nstate==S1) begin
                en_cnt <=1;
            end
            else
                en_cnt <= 0;
            
    end
endmodule
